1. Field of the Invention
The present invention relates to integrated circuits to be utilized in such products as a semi-custom LSI or a micro-processor, and more particularly, to such integrated circuits particularly suitable for large-scale integrated, high-speed processing applications.
2. Description of the Background Art
The development of high-speed and large-scale integrated circuits prompted more densely laid out integrated circuit designs.
In FIG. 1, one such conventional layout is shown, in which two function blocks 1 capable of performing some required functions are controlled by a control block 3. Each of the function blocks 1 may contain, for example, a arithmetic logic operator circuit or a barrel shifter for a micro-processor. The n bit input data are provided to one of the function blocks 1, and the n bit output data are produced from another one of the function blocks 1, as shown in FIG. 1. In other words, the data are transmitted in the Y-direction.
In such a case, the control signals for controlling the operation of the function blocks 1 from the control block 3 are usually transmitted, in and out of the function blocks 1, in the X-direction, as shown in FIG. 1. Consequently, the control block 3 is usually located in to either the left or the right of the function blocks 1, as in FIG. 1.
Here, the control signals cannot be propagated through the element area in the function block. This is because for transmitting a number of control signals through the element area, as many different types of routings are required.
For this reason, there is usually provided routing areas 5 sandwiching each function block 1 in the Y-direction, as in FIG. 1, through which the control signals are transmitted between the function blocks 1 and the control block 3 by routings 7, as shown in FIG. 2.
This layout, however, necessitates the extension of the routing areas 5 in the Y-direction when the number of routings 7 are to be increased. Since the longer routings 7 (in the Y-direction) are needed for the routing areas 5 extended in the Y-direction, the routing load will also increase in such a case, which can lead to the slowing down of the control signal transmission.
Moreover, when all the routings 7 are to be provided from one control block 3, there appears a dead space in the routing areas 5 at which there are no routings, as in FIG. 2. Obviously, this dead space becomes particularly large when the routing areas 5 are extended in the Y-direction. Thus, when the number of control signals is increased, the efficiency of area utilization is considerably deteriorated.
On the other hand, the control signals usually require buffer circuits because of their large load. When such buffer circuits are not to be incorporated inside either the function blocks 1 or the control block 3, a buffer block 8 is provided between the function blocks 1 and the control block 3, as shown in FIG. 3, where each subdivision inside the buffer block 8 represents one buffer circuit for one control signal, and the buffer block 8 comprises such individual buffer circuits arranged along the Y-direction.
In such a case, the size of the entire integrated circuit in the Y-direction depends on the pitch in the Y-direction between adjacent buffer circuits inside the buffer block 8. In particular, when the number of control signals is increased, a corresponding increase in the number of buffer circuits necessitates the extension in the Y-direction of routing crank areas 9 between the buffer block 8 and the function blocks 1 as well as between the buffer block 8 and the control block 3. This can lead to the appearance of dead blocks 6 below the function blocks 1 and the control block 3, as in FIG. 3. Thus, again, when the number of control signals is increased, the efficiency of area utilization is considerably deteriorated.